A semiconductor device is generally manufactured, for example as shown in FIG. 15, by die bonding a semiconductor chip 21 on a die pad 22 of a lead frame, wire bonding an electrode pad 21a to a lead 23 of the lead frame with a gold wire 24, and forming a package 25 by molding a resin.
And as a means to achieve down sizing, thinning and weight lightening, a chip size package has been employed, as shown in FIG. 16 or 17, in which the electrode pads 21a around the semiconductor chip 21 are disposed on the semiconductor chip 21, thereafter solder balls are formed. Namely, an example shown in FIG. 16 represents a technology including steps of forming interconnections (not shown in the figure) on one surface of an interposer 26 made of a ceramic substrate, an organic substrate made of polyimide or the like, a film tape or the like, connecting the electrode pad 21a of the semiconductor chip 21 to the above-described interconnection by wire bonding using the gold wire 24 or the like, forming external electrodes 27, on a back surface of the interposer 26, made of solder balls or the like connected to each of the interconnections and coating a side of the semiconductor chip 21 with a resin 25. And, an example shown in FIG. 17 is formed by connecting the electrode pad 21a of the semiconductor chip 21 to the interconnection not by wire bonding, but by connecting directly a solder bump 21b to the interconnection of the interposer 26 after forming the solder bump 21b on the electrode pad (not shown in the figure). The other structures are the same as that in the example shown in FIG. 16. Reference number 28 represents a resin layer with which the semiconductor chip is fixed.
Since electrode pads formed around a semiconductor chip with very small spacing are disposed to an entire area of the semiconductor chip by using an interposer explained above, the semiconductor chip can be connected directly to the circuit board. For example, being accompanied with a promotion of high integration and down sizing of semiconductor chips, the electrode pads are located around the semiconductor chip with a spacing of approximately 100 to 200 μm. On the contrary, since interconnections of a circuit board, on which the semiconductor chip is mounted, have a spacing of approximately 0.5 mm, the semiconductor chip can not be connected to the circuit board directly even if bump electrodes are formed on the electrode pads of the semiconductor chip. But by using the interposer, as electrodes can be disposed in the entire interposer, the semiconductor chip can be mounted directly to the circuit board.
Although down sizing becomes possible by using a chip size package as described above, the interposer and a process of connecting to it is necessary. The semiconductor device by using the interposer is generally more expensive compared to that by using a lead frame, because an amount of distribution, that is, an amount of production is small, or fine fabrication is occasionally demanded. Further, wire bonding between the interposer and the semiconductor chip is performed not in a lump but one by one, and, although plated bumps by a general electroplating technique can be formed in a lump, expensive equipments are indispensable like a stepper apparatus, and apparatuses for photoresist coating, photoresist developing, lithography and so on in a process of forming barrier metals. Therefore, there exists a problem such that the chip size package is expensive, even though down sizing, thinning and weight lightening can be achieved.
On the other hand, in order to solve the problem described above, the present inventor disclosed a method for manufacturing a down sized and thinned semiconductor device which included processes of relocating electrode pads on a semiconductor substrate, on which an electronic circuit is formed, by interconnection so as to be disposed in an area of an entire surface of a semiconductor chip, forming a barrier metal layer on the electrode pad by an electroless plating technique, forming a solder core thereon, exposing the solder core by grinding a resin layer after forming the resin layer on an entire surface, forming a solder bump on the exposed solder core, and forming a resin layer on the back surface of the semiconductor substrate, after thinning the semiconductor substrate by grinding a back surface of the semiconductor substrate (cf. PATENT DOCUMENT 1).
PATENT DOCUMENT 1: Japanese Patent Application Laid-Open No. 2003-338515